Reducing Memory Controller Transaction Queue Size in Scalable Memory Systems

Scalable memory systems provide scalable bandwidth to the core growth demands in multicores’ and embedded systems’ processors. In these systems, as memory controllers (MCs) are scaled, memory traffic per MC is reduced, therefore transaction queues become shallower. As a consequence, there is an opportunity to explore transaction queue utilization and its impact on energy. In this paper we propose to evaluating the performance and energy-per-bit impact of the number of entries of the transaction queues along the MCs in these systems. Preliminary results show that reducing 50% of the number of entries, bandwidth and energy-per-bit levels are not affected, while if reducing them of 93%, bandwidth is reduced of 91% and energy-per-bit levels are increased of 780%.

http://www.worlditcongress.org/2015jeju/proceeding...